Method of operating non-volatile memory array

ABSTRACT

A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-−2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of patent application Ser. No.11/621,095, filed on Jan. 8, 2007, now allowed, which is a divisionalapplication of patent application Ser. No. 10/904,478, filed on Nov. 12,2004 and allowed as U.S. Pat. No. 7,180,128, granted on Feb. 20, 2007,which claims the priority benefit of Taiwan patent application serialno. 93113274, filed on May 12, 2004 and is now allowed. The entirety ofeach of the above-mentioned patent applications is hereby incorporatedby reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a method of manufacturinga non-volatile memory and a method of operating a non-volatile memoryarray.

2. Description of Related Art

Electrically erasable programmable read only memory (EEPROM) is a typeof non-volatile memory that allows multiple data reading, writing anderasing operations. In addition, the stored data will be retained evenafter power to the device is removed. With these advantages, it has beenbroadly applied in personal computer and electronic equipment.

A typical EEPROM has a floating gate and a control gate fabricated usingdoped polysilicon. To prevent erroneous reading resulting from theover-erasure of the EEPROM during an erasing operation, a select gate isset up above the substrate on the sidewall of the control gate and thefloating gate forming a so-called split-gate structure.

At present, the industry has developed an AG-AND memory cell arrayfabricated using a split-gate memory cells (refer to U.S. Pat. No.6,567,315). FIG. 1 is a schematic cross-sectional view of a portion of aconventional AG_AND memory cell structure. As shown in FIG. 1, theAG-AND memory cell structure includes a substrate 100, a well region102, an auxiliary gate transistor Qa1 (Qa2), a memory device Qm1 (Qm2)and source/drain regions 104 a, 104 b (104 c) in the substrate 100 onone side of the auxiliary gate transistor Qa1 (Qa2) and the memorydevice Qm1 (Qm2) respectively. The auxiliary gate transistor Qa1 (Qa2)includes an auxiliary gate 106 a and the memory device Qm1 (Qm2)includes a floating gate 108 a (108 b) and a word line 110. The wordline 110 serves as a control gate for the memory device Qm1 (Qm2). Theauxiliary gate transistor Qa1 (Qa2) and the memory device Qm1 (Qm2)together form a memory cell Q1 (Q2). In an AG-AND array, neighboringmemory cells in the row direction use a common source/drain region.

To program memory cell Q1 of the aforementioned AG-AND memory cellarray, a 13V bias voltage is applied to the word line 110, a 1V biasvoltage is applied to the auxiliary gate 106 a, a 0V bias voltage isapplied to the source/drain region 104 a and a 5V bias voltage isapplied to the source/drain region 104 b. Thus, electrons are injectedinto the floating gate 108 a of the memory device Qm1 to program thememory cell Q1. Because a bias voltage is not applied to the auxiliarygate 106 b, the memory cell Q2 is not programmed.

However, in the aforementioned AG-AND memory cell structure, asource/drain region (104 a, 104 b or 104 c) is formed in the substrate100 on each side of the memory cell Q1 (Q2). To prevent the source/drainregion (104 a, 104 b or 104 c) from getting too close to the conductivechannels underneath the memory cell, the source/drain regions (104 a,104 b or 104 c) have to be separate from each other by a definitedistance. This precludes any further miniaturization of the memory cellarray.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a non-volatile memory,a non-volatile memory array and a manufacturing method thereof capableof simplifying the fabrication of non-volatile memory array. Thenon-volatile memory is also programmed using a source-side injection(SSI) method so that the average programming speed of the memory cellsis increased and overall performance of the memory is improved.

The present invention is also directed to a non-volatile memory, anon-volatile memory array and a manufacturing method thereof capable ofincreasing the overlapping area between the floating gate and thecontrol gate inside the memory. Hence, the coupling ratio of the gatesinside the memory is increased and overall performance of the memory isimproved.

The present invention is also directed to a non-volatile memory, anon-volatile memory array and a manufacturing method thereof capable ofminiaturizing the memory cells and increasing overall level ofintegration of devices.

According to an embodiment of the present invention, the non-volatilememory includes a substrate, a first row of memory cells, a firstsource/drain region and a second source/drain region. The first row ofmemory cells further includes a plurality of stacked gate structures, aplurality of spacers, a plurality of control gates, a plurality offloating gates, a plurality of inter-gate dielectric layers and aplurality of tunneling dielectric layers. The stacked gate structuresare formed on the substrate and separated from each other by a gap. Eachstacked gate structure includes, from the substrate surface upward, aselect gate dielectric layer, a select gate and a cap layer. The spacersare disposed on the sidewalls of the stacked gate structuresrespectively. The control gates are disposed over the substrate fillingthe gap between every pair of neighboring stacked gate structures.Furthermore, the control gates are connected together through a controlgate line. The floating gates are disposed between every pair ofneighboring stacked gate structures between the control gate and thesubstrate respectively. The inter-gate dielectric layers are disposedbetween the control gates and the floating gates respectively. Thetunneling dielectric layers are disposed between the floating gates andthe substrate. The first source/drain region and the second source/drainregion are disposed in the substrate on each side of the first row ofmemory cells.

The aforementioned non-volatile memory further includes a second row ofmemory cells, a second source/drain region and a third source/drainregion disposed on the substrate. The second row of memory cells isconnected with the first row of memory cells by the second source/drainregion, wherein the second row of memory cells have structures identicalto the first row of memory cells. The third source/drain region isdisposed in the substrate on the side of the second row of memory cellscorresponding to the second source/drain region.

Since no contacts and device isolation structures are formed betweenvarious rows of memory cells in the non-volatile memory according to anembodiment of the present invention, the level of integration of thememory array is increased.

The present invention is also directed to a non-volatile memory arrayincluding a substrate, a plurality of rows of memory cells, a pluralityof control gate lines, a plurality of select gate lines, a plurality ofsource lines and a plurality of drain lines. The rows of memory cellsare aligned to form a memory array. Each row of memory cells furtherincludes a plurality of stacked gate structures disposed on thesubstrate and separated from each other by a gap. Each stacked gatestructure includes, from the substrate surface upward, a select gatedielectric layer, a select gate and a cap layer. The spacers aredisposed on the sidewalls of the stacked gate structures. The floatinggates are disposed in the gaps between every pair of neighboring stackedgate structures. The tunneling dielectric layer is disposed between thefloating gate and the substrate. The control gates are disposed betweenevery pair of neighboring stacked gate structures above the floatinggate. The inter-gate dielectric layers are disposed between the controlgates and the floating gates. The source/drain regions are disposed inthe substrate just outside the outermost two stacked gate structures.The control gate lines connect all the control gates in the same row ofmemory cells. The select gate lines connect all the select gates in thesame column of memory cells. The source lines connect all the sourceregions in the same column. The drain lines connect all the drainregions in the same column.

In the aforementioned non-volatile memory array, the memory array can befurther divided into at least a first memory block and a second memoryblock. The drains of each row of memory cells within the first memoryblock are connected together through a first drain line. Similarly, thedrains of each row of memory cells within the second memory block areconnected together through a second drain line. Furthermore, both thefirst memory block and the second memory block use a common source line.

The aforementioned memory cell array may utilize source-side injectionto inject electrons into the floating gate of a selected memory cell andprogram the selected memory cell. Furthermore, the Fowler-Nordheimtunneling effect is utilized to pull the electrons trapped within thefloating gate of the memory cells into the substrate so that all thedata within the memory array are erased.

According to an embodiment of the present invention, there is no gapbetween the various memory cell structures in the non-volatile memoryarray. Hence, the level of integration of the memory cell array isincreased.

Since no contacts and device isolation structures are formed betweenvarious rows of memory cells in the non-volatile memory array of thepresent invention, the level of integration of the memory array isincreased.

The present invention is also directed to a method of fabricating anon-volatile memory. First, a substrate is provided. A plurality ofstacked gate structures is formed on the substrate. Each stacked gatestructure includes a select gate dielectric layer, a select gate and acap layer. Thereafter, a source region and a drain region are formed inthe substrate. The source region and the drain region are separated fromeach other by at least two stacked gate structures. A tunnelingdielectric layer is formed over the substrate and then a firstconductive layer is formed over the tunneling dielectric layer. Thefirst conductive layer is patterned to form a plurality of floating gatein the gaps between the stacked gate structures. After forming aninter-gate dielectric layer over the substrate, a second conductivelayer is formed over the substrate. The second conductive layer ispatterned to form a plurality of mutually linked control gates in thegaps between neighboring stacked gate structures.

According to an embodiment of the present invention, the tunnelingdielectric layer can be formed by performing a thermal oxidationprocess. Furthermore, an additional insulating layer may also be formedover the source/drain region.

According to an embodiment of the present invention, floating gateshaving concave opening is produced to increase the overlapping areabetween the floating gate and the control gate. Hence, the gate-couplingratio of the memory cells is increased and the required operatingvoltage is lowered. Ultimately, the average operating speed of thememory cell is increased.

Furthermore, a thick insulating layer is also formed over the sourceregion and the drain region. The insulating layer isolates the floatinggate and the control gate above the source region and the drain regionso that their effects on the source and the drain region are minimized.Since there is no need to perform an extra processing operation toremove the floating gate and the control gate above the source and thedrain, the process of fabricating the non-volatile memory is very muchsimplified.

In addition, no device isolation structures are set up between variousrows of memory cells. Hence, the number of processing steps can bereduced and the level of integration of the memory array can beincreased.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross-sectional view of a portion of aconventional AG_AND memory cell structure.

FIG. 2A is a top view of a non-volatile memory array according to anembodiment of the present invention.

FIG. 2B is a schematic cross-sectional view along line A-A′ of FIG. 2A.

FIGS. 3A through 3E are schematic cross-sectional views along a lineA-A′ of FIG. 2A showing the steps for fabricating a non-volatile memoryaccording to an embodiment of the present invention.

FIG. 4 is a simplified circuit diagram of a non-volatile memory arrayaccording to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to the present embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

FIG. 2A is a top view of a non-volatile memory array according to anembodiment of the present invention. FIG. 2B is a schematiccross-sectional view along line A-A′ of FIG. 2A. As shown in FIGS. 2Aand 2B, the memory array can be divided into a first memory block 200 aand a second memory block 200 b. The first memory block 200 a and thesecond memory block 200 b use a common source region 220 (the sourceline S). In the following, only the row of memory cells 200 a isdiscussed.

As shown in FIG. 2A, the non-volatile memory array of the presentinvention includes a substrate 200, a plurality of rows of memory cellsQL1˜QL4, a plurality of control gate lines CG1˜CG4, a plurality ofselect gate lines SG1˜SG5, a source line S and a drain line D.

The rows of memory cells QL1˜QL4 are aligned to form a memory array. Thecontrol gate lines CG1˜GC4 connects the control gates of the memorycells in the same row. The select gate lines SG1˜SG5 connects the selectgates of the memory cells in the same column. The source line S connectsall the source regions of the rows of memory cells in the same column.The drain line D connects all the drain regions of the rows of memorycells in the same column.

In the following, the rows of non-volatile memory cell structure areexplained using a single row of memory cells QL1 as an example.

As shown in FIGS. 2A and 2B, the non-volatile memory structure of thepresent invention includes at least a substrate 200, a plurality ofstacked gate structures 202 a˜202 e (each of these stacked gatestructures 202 a˜202 e includes, from the substrate surface upward, aselect gate dielectric layer 204, a select gate 206 and a cap layer208), a plurality of spacers 210, a plurality of tunneling dielectriclayer 212, a plurality of floating gates 214 a˜214 f, a plurality ofcontrol gates 216 a˜216 f, a plurality of inter-gate dielectric layers218, a plurality of source regions 210 and a plurality of drain regions222.

The substrate 200 is a silicon substrate, for example. The stacked gatestructures 202 a˜202 e are disposed on the substrate 200. Each stackedgate structure is a linear strip having a thickness between 2000 Å to3500 Å, for example. The select gate dielectric layer 204 having athickness between 160 Å˜170 Å is formed by silicon oxide, for example.The select gate 206 having a thickness between 600 Å to 1000 Å is formedby doped polysilicon, for example. The cap layer 208 having a thicknessbetween 1000 Å to 1500 Å is formed by silicon oxide, for example. Thespacer is disposed on the sidewalls of the stacked gate structures 202a˜202 e. The spacer is formed by silicon oxide or silicon nitride, forexample.

The control gates 216 a˜216 d are disposed on the substrate 200 fillingthe gap between every pair of neighboring stacked gate structures 202a˜202 e. Furthermore, the control gates 216 a˜216 d are connectedtogether through the control gate lines 216. The control gates 216 a˜216d and the control gate lines 216 are formed together as an integrativeunit. In other words, the control gates 216 a˜216 d extend over thestacked gate structures and link with each other to form the controlgate lines 216. The control gate lines 216 is roughly perpendicular tothe stacked gate structures 202 a˜202 e. The control gates 216 a˜216 dare formed by doped polysilicon, for example.

The floating gates 214 a˜214 d are disposed in the gaps between everypair of neighboring stacked gates 202 a˜202 e and positioned between thecontrol gates 216 a˜216 d and the substrate 200. Each of the floatinggates 214 a˜214 d has a concave opening 215, for example. Furthermore,the upper surface of the floating gates 214 a˜214 d are located on oneside of the stacked gate structure 202 a˜202 e between the upper surfaceof the select gate 206 and the upper surface of the cap layer 208.Typically, the floating gates 214 a˜214 d are formed by dopedpolysilicon, for example.

The tunneling dielectric layer 212 is disposed between the floatinggates 214 a˜214 d and the substrate 200. Typically, the tunnelingdielectric layer is a silicon oxide layer having a thickness between 60Å˜90 Å, for example. The inter-gate dielectric layer 218 is disposedbetween the control gates 216 a˜216 d and the floating gates 214 a˜214d. Typically, the inter-gate dielectric layer 218 is a composite layerincluding a silicon oxide, silicon nitride and silicon oxide layer eachhaving a thickness of about 70A. Obviously, the inter-gate dielectriclayer 218 can be a composite layer including a silicon oxide and asilicon nitride layer. The inter-gate dielectric layer 218 also coversthe upper surface of the stacked gate structures 202 a˜202 e.

The stacked gate structures 202 a˜202 e, the spacers 210, the tunnelingdielectric layers 212, the floating gates 214 a˜214 d, the control gates216 a˜216 d and the inter-gate dielectric layer together constitute arow of memory cells 230. The source region 222 and the drain region 220are disposed in the substrate 200 on each side of the row of memorycells 230. For example, the drain region 220 is disposed in thesubstrate 200 on one side of the stacked gate structure 202 a while thesource region 222 is disposed in the substrate 200 on one side of thestacked gate structure 202 e. In other words, the drain region 220 andthe source region 222 are disposed in the substrate 200 just outside thetwo outermost stacked gate structures (202 a and 202 e) of the row ofconnected memory cells 230.

In the aforementioned row-connected memory cell structure 230, thestacked structures including control gates 216 a˜216 d and floatinggates 214 a 214 d respectively and the stacked gate structures 202 a˜202d together form memory cell structures 226 a˜226 d. The stacked gatestructure 202 e closest to the source region 222 also serves as aswitching transistor. Because there is no gap between memory cellstructures 226 a˜226 d and the stacked gate structure 202 e, the row ofmemory cells can have a higher level of integration. Furthermore, aninsulating layer 224 is disposed over the drain region 220 and thesource region 222 respectively. The insulating layer 224 is fabricatedusing silicon oxide, for example. The insulating layer 224 serves toisolate the stacked gate structure including the control gate 216 f andthe floating gate 214 f and the drain region 220 as well as the stackedgate structure including the control gate 216 e and the floating gate214 e and the source region 222. Hence, the operation of the controlgate 216 f and the floating gate 214 f above the drain region 220 andthe control gate 216 e and the floating gate 214 e above the sourceregion 222 have no effect on the drain region 220 and the source region222 respectively.

Furthermore, because the floating gates 214 a˜214 d all have a concaveopening 215, overlapping area between various floating gates 214 a˜214 dand their corresponding control gates 216 a˜216 d is increased therebyincreasing their gate-coupling ratio. In other words, the memory cellscan have a lower operating voltage, a higher operating speed and abetter overall performance.

In the aforementioned embodiment, four memory cell structures 226 a˜226d are serially connected together. Clearly, the number of memory cellsthat are serially connected together may vary according to actualrequirements. For example, the same control gate line may link together32 to 64 memory cell structures.

Furthermore, in the memory cell array shown in FIG. 2A, no deviceisolation structures or contacts are fabricated between various rows ofmemory cells. Thus, the level of integration of the memory array isincreased.

FIGS. 3A through 3E are schematic cross-sectional views along a lineA-A′ of FIG. 2A showing the steps of fabricating a non-volatile memoryaccording to one embodiment of the present invention. First, as shown inFIG. 3A, a substrate 300 such as a silicon substrate is provided. Aplurality of stacked gate structures 308 each including a dielectriclayer 302, a conductive layer 304 and a cap layer 306 is formed over thesubstrate 300. The stacked gate structures 308 are formed, for example,by depositing dielectric material, conductive material and cap materialin sequence over the substrate 300 and patterning the dielectric layer,the conductive layer and the cap layer in photolithographic and etchingprocesses thereafter. The dielectric layer is a silicon oxide layerformed, for example, by performing a thermal oxidation process. Theconductive layer is a doped polysilicon layer formed, for example, byperforming a chemical vapor deposition process and implanting ions intothe doped polysilicon layer thereafter. The cap layer is a silicon oxidelayer formed, for example, by performing a chemical vapor depositionprocess using tetra-ethyl-ortho-silicate (TEOS)/ozone (O₃) as thegaseous reactants. The conductive layer 304 serves as a select gate andthe dielectric layer 302 serves as a select gate dielectric layer.

As shown in FIG. 3B, a spacer 310 is formed on the sidewall of thestacked gate structures 308. The spacers 310 are silicon oxide orsilicon nitride layers are formed, for example, by depositing insulatingmaterial over the substrate and performing an anisotropic ion etchingprocess thereafter. A mask layer 312 is formed over the substrate 300.The mask layer 312 has openings 314 that expose the areas on thesubstrate 300 for forming a source region 316 and a drain region 318.Typically, the mask layer 312 is a photoresist layer. Thereafter, usingthe mask layer 312 as a mask, a source region 316 and a drain region 318are formed in the substrate 300 by performing an ion implantationprocess, for example. The source region 316 and the drain region 318 areseparated from each other by at least two stacked gate structures 308.

After removing the mask layer 312, a tunneling dielectric layer 320 isformed over the substrate 300 and an insulating layer 322 is formed overthe source region 316 and the drain region 318. The tunneling dielectriclayer 320 and the insulating layer 322 are silicon oxide layer formed byperforming a thermal oxidation process, for example. The source region316 and the drain region contain dopants, the oxidation rate is higherthan other areas free of dopants since the insulating layer 322 isformed over the source region 316 and the drain region 318.Consequently, the insulating layer 322 has a thickness greater than thetunneling dielectric layer 320.

As shown in FIG. 3C, another conductive layer 324 is formed over thesubstrate 300. The conductive layer is a doped polysilicon layer formed,for example, by depositing an undoped polysilicon layer over thesubstrate in a chemical vapor deposition and then performing an ionimplantation process. The conductive layer 324 is a conformal layer overthe substrate 300 such that the gap between neighboring stacked gatestructures 308 is unfilled.

As shown in FIG. 3D, the conductive layer 324 is patterned to form aplurality of floating gates 326. The floating gates 326 are formed, forexample, by depositing a material over the substrate 300 to form amaterial layer (not shown) that completely fills the gaps between thestacked gate structures 308. The material layer has an upper surfacelying between the upper surface of the cap layer 306 and the uppersurface of the conductive layer 304. The material layer is a photoresistlayer or an anti-reflection coating formed, for example, by spin coatingto form the material layer and then etching back the material layer.Thereafter, using the material layer as a mask, a portion of theconductive layer 324 is removed. Hence, the upper surface of theconnective sections between the conductive layer 324 and the stackedgate structures 308 is located between the upper surface of theconductive layer 304 and the cap layer 306. After removing the materiallayer, photolithographic and etching processes are carried out to removea portion of the conductive layer 324 so that the conductive layer 324is dissected into a plurality of blocks thereby forming floating gates326 between the stacked gate structures 308. Each floating gate 326 hasa concave opening 327 for increasing the overlapping area with asubsequently formed control gate.

In the process of forming the floating gates 326 according to anotherembodiment, a portion of the conductive layer 324 can be directlyremoved by performing an etching back process instead of using thematerial layer so that the conductive layer 324 has an upper surfacebetween the conductive layer 304 and the cap layer 306. Thereafter, aportion of the conductive layer 324 is removed to dissect the conductivelayer 324 into separate blocks of floating gates 326.

In the process of forming the floating gates 326 according to yetanother embodiment, the step of dissecting the conductive layer 324 intoa plurality of blocks is skipped altogether. Instead, the conductivelayer 324 is dissected to form a plurality of floating gates 326 lateron in a subsequent process for fabricating the control gate by using thecontrol gate as a mask.

Thereafter, an inter-gate dielectric layer 328 is formed over thesubstrate 300. The inter-gate dielectric layer 328 is a silicon oxide,silicon nitride, silicon oxide composite layer, for example. Theinter-gate dielectric layer is formed, for example, by performing athermal oxidation process to form a silicon oxide layer and then forminga silicon nitride layer and another silicon oxide layer in sequence in achemical vapor deposition process.

As shown in FIG. 3E, another conductive layer (not shown) is formed overthe substrate 300. The conductive layer completely fills the gapsbetween the stacked gate structures 308. The conductive layer is formed,for example, by depositing conductive material over the substrate andperforming a chemical-mechanical polishing or an etching back process toplanarize the conductive material layer. The conductive layer is a dopedpolysilicon layer formed, for example, by depositing undoped polysiliconmaterial to form an undoped polysilicon layer in a chemical vapordeposition process and then implanting ions to transform the undopedpolysilicon layer into a doped polysilicon layer. Thereafter, theconductive layer is patterned to form a word line 330 such that the wordline 330 fills the gaps between the stacked gate structures 308. Thecontrol gate line 330 above the floating gate 326 serves as a controlgate 330 a. In other words, the control gate 330 a extends into thesurface of the stacked gate structure 308 to connect with each other.Thereafter, a few more steps are still required to complete the processof fabricating the memory array. Since these are conventional steps,detailed descriptions are omitted.

In the aforementioned embodiment, all floating gates 326 have a concaveopening so that the overlapping area between the floating gate 326 andthe control gate 330 a is increased. Hence, the gate-coupling ratio ofthe memory cells is increased and the required operating voltage islowered. Ultimately, the average operating speed of the memory cell isincreased.

Furthermore, a thick insulating layer 322 is also formed over the sourceregion 316 and the drain region 318. The insulating layer 322 isolatesthe floating gate 326 and the control gate 330 a above the source region316 and the drain region 318 so that their effects on the source region316 and the drain region 318 are minimized.

Since there is no need to perform an extra processing operation toremove the floating gate 326 and the control gate 330 a above the source316 and the drain 318, the process of fabricating the non-volatilememory is simplified.

In addition, no device isolation structures are set up between variousrows of memory cells. Hence, the number of processing steps can bereduced and the level of integration of the memory array can beincreased.

In the aforementioned embodiment, four memory cell structures areserially connected together. Clearly, the number of memory cells thatare serially connected together in a row may vary according to actualrequirements. For example, a single bit line may link together 32 to 64memory cell structures. Furthermore, the method of fabricating a row ofmemory cells can be directly applied to manufacture an entire memorycell array.

FIG. 4 is a simplified circuit diagram of a non-volatile memory arrayaccording to the present invention. In FIG. 4, the memory is dividedinto a first memory block BLOCK1 and a second memory block BLOCK2. Inthe following, the memory block BLOCK1 having altogether 16 memory cellsis used as an example to illustrate the operation of a memory array inthe present invention.

As shown in FIG. 4, there are 16 memory cells Q11˜Q44, four switchingtransistors T1˜T4, five select gate lines SG1˜SG5, four control gatelines CG1˜CG4, a source line S and a drain line D in the memory blockBLOCK1. Each of the memory cells Q11˜Q44 has a select gate, a controlgate and a floating gate. The source line S and the drain line extend inthe column direction. In the column direction, the drain line D and thesource line S link up a plurality of memory cells. Each row of memorycells includes four memory cells and a switching transistor seriallyconnected together. For example, the memory cells Q11˜Q14 and theswitching transistor T1 are serially connected together. Similarly, thememory cells Q21˜Q24 and the switching transistor T2 are seriallyconnected together, the memory cells Q31˜Q34 and the transistor T3 areserially connected together and the memory cells Q41˜Q44 and thetransistor T4 are serially connected together.

The control gate lines CG1˜CG4 connect all the control gates of thememory cells in various rows. For example, the control gate line CG1connects the control gates of the memory cells Q11˜Q14. Similarly, thecontrol gate line CG2 connects the control gates of the memory cellsQ21˜Q24, the control gate line CG3 connects the control gates of thememory cells Q31˜Q34 and the control gate line CG4 connects the controlgates of the memory cells Q41˜Q44.

The select gates SG1˜SG4 connect the select gates of the memory cells invarious columns. For example, the select gate SG1 connect the selectgates of the memory cells Q1˜Q41. Similarly, the select gate SG2 connectthe select gates of the memory cells Q12˜Q42, the select gate SG3connect the select gates of the memory cells Q13˜Q43 and the select gateSG4 connect the select gates of the memory cells Q14˜Q44. In addition,the select gate SG5 connects the gates of the switching transistorsT1˜T4 in the same column.

To program the memory cells Qn2, for example, a 5V bias voltage isapplied to the source line S, a 1.5V bias voltage is applied to theselected gate line SG2, an 8V bias voltage is applied to thenon-selected gate lines SG1, SG3 and SG4, an 8V bias voltage is appliedto the select gate line SG5, a 10˜12V bias voltage is applied to thecontrol gate line CG1, a 0˜−2V bias voltage is applied to thenon-selected control gate lines CG2, CG3 and CG4 and the substrate andthe drain line D is connected to a ground. Hence, a source-sideinjection (SSI) is triggered to inject electrons into the floating gatesof the memory cells thereby programming the memory cells Qn2.

To read data from the memory, a 0V bias voltage is applied to the sourceline S, a 4.5V bias voltage is applied to the select gate lines SG1˜SG5,a 3V bias voltage is applied to the control gate line CG1 and a 2V biasis applied to the drain line D. Because the channel of memory cells withfloating gate having a net negative charge will block the passage of acurrent and the channel of memory cells with floating gate having a netpositive charge will facilitate the passage of a current, the channelon/off state or the size of the channel current can be used to determinethe binary data ‘1’ or ‘0’ stored inside the memory cells.

To erase data from the memory cells, a −20V bias voltage is applied tothe control gate line CG1 and a 0V bias voltage is applied to thesubstrate so that the Fowler-Nordheim (F-N) tunneling effect can beutilized to pull trapped electrons within the floating gate of thememory cells into the substrate.

In the operating mode of the memory cell array according to the presentinvention, the hot carrier effect is utilized to program a single bit ofdata into a single memory cell but the F-N tunneling effect is utilizedto erase the data in the entire memory cell array. Hence, the electroninjection efficiency is relatively high. In other words, the operatingmemory cell current is lowered and the operating speed is increased.With a reduction in the memory cell current, the average powerconsumption of the memory chip is reduced.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A method of operating a non-volatile memory array, the non-volatilememory array comprising: a substrate; a plurality of rows of memorycells, wherein each row of memory cells includes a plurality of stackedgate structures separated from each other by a gap, and each stackedgate structure includes a select gate, a plurality of floating gatesdisposed in the gap between every pair of neighboring stacked gatestructures, a plurality of control gates disposed between every pair ofneighboring stacked gate structures and positioned above the floatinggate, and a pair of source/drain region disposed in the substrate oneach outer side of the row of the memory cells; a plurality of controlgate lines connected with the control gates in the same row; a pluralityof select gate lines connected with the select gates in the same column;a plurality of source lines connected with the source regions in thesame column; and a plurality of drain lines connected with the drainregions in the same column, the operating method comprising: applying 5Vvoltage to a selected source line, 1.5V voltage to a selected selectgate line, 8V voltage to non-selected select gate lines, 10-12V voltageto a selected control gate line and 0-−2V voltage to non-selectedcontrol gate lines and the substrate; and grounding the drain lines sothat source-side injection (SSI) is triggered to inject electrons intothe floating gate of the selected memory cell in a programmingoperation.
 2. The method of claim 1, further comprising: applying 0Vvoltage to the source lines, 4.5V voltage to the select gate lines, 3Vvoltage to the selected control gate line and 2V voltage to the drainlines to read data from the memory cells.
 3. The method of claim 1,further comprising: applying −20V voltage to the control gate lines and0V voltage to the substrate so that the Fowler-Nordheim (F-N) tunnelingeffect can be induced to erase all data within the memory array.